From: a...@cs.rice.edu (Alan Cox)
Subject: SMP users please read
Date: 1999/03/04
Message-ID: <19990304010923.A33835@nonpc.cs.rice.edu>#1/1
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There is an SMP-specific bug in pmap_remove_all. Specifically, it may
fail to perform a TLB invalidation on the other processor(s) when one is
in fact necessary.
I don't have an SMP to test this, so would some of you with SMPs
please do a sanity test on this patch? In effect, the patch disables
an optimization for uniprocessors that doesn't work under our current
SMP code. I will commit it as soon as I hear a few positive reports.
Thanks,
Alan
Index: pmap.c
===================================================================
RCS file: /home/ncvs/src/sys/i386/i386/pmap.c,v
retrieving revision 1.223
diff -c -r1.223 pmap.c
*** pmap.c 1999/02/19 14:25:33 1.223
--- pmap.c 1999/03/04 06:52:21
***************
*** 1991,2001 ****
--- 1991,2005 ----
if (pmap_track_modified(pv->pv_va))
vm_page_dirty(ppv->pv_vm_page);
}
+ #ifdef SMP
+ update_needed = 1;
+ #else
if (!update_needed &&
((!curproc || (vmspace_pmap(curproc->p_vmspace) == pv->pv_pmap)) ||
(pv->pv_pmap == kernel_pmap))) {
update_needed = 1;
}
+ #endif
TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist);
TAILQ_REMOVE(&ppv->pv_list, pv, pv_list);
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From: Alan Cox <a...@cs.rice.edu>
Subject: SMP users (important)
Date: 1999/04/02
Message-ID: <19990402124153.H14114@nonpc.cs.rice.edu>#1/1
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I've committed the basic infrastructure to improve TLB management
on SMPs. Translation: this will lead to the elimination of a LOT
of interprocessor interrupts to invalidate TLB entries. I'll be
"turning on" the new mechanisms slowly so we can carefully debug
each step and (hopefully) avoid any problems.
Now, if you're not using Luoqi's patches to enable multithreaded
address spaces, you can stop reading here. If you are, you'll
need to patch i386/i386/swtch.s as follows:
Index: i386/i386/swtch.s
===================================================================
RCS file: /home/ncvs/src/sys/i386/i386/swtch.s,v
retrieving revision 1.78
diff -c -r1.78 swtch.s
*** swtch.s 1999/04/02 17:59:39 1.78
--- swtch.s 1999/04/02 18:37:29
***************
*** 466,472 ****
#else
xorl %eax, %eax
#endif /* SMP */
! btrl %eax, VM_PMAP+PM_ACTIVE(%edx)
movl P_ADDR(%ecx),%edx
--- 466,473 ----
#else
xorl %eax, %eax
#endif /* SMP */
! movl VM_PMAP(%edx), %edx
! btrl %eax, PM_ACTIVE(%edx)
movl P_ADDR(%ecx),%edx
***************
*** 690,696 ****
#else
xorl %eax, %eax
#endif
! btsl %eax, VM_PMAP+PM_ACTIVE(%ebx)
/* restore context */
movl PCB_EBX(%edx),%ebx
--- 691,698 ----
#else
xorl %eax, %eax
#endif
! movl VM_PMAP(%ebx), %ebx
! btsl %eax, PM_ACTIVE(%ebx)
/* restore context */
movl PCB_EBX(%edx),%ebx
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From: "John S. Dyson" <dy...@iquest.net>
Subject: Re: SMP users (important)
Date: 1999/04/03
Message-ID: <199904031316.IAA45781@y.dyson.net>#1/1
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Alan Cox said:
>
> I've committed the basic infrastructure to improve TLB management
> on SMPs. Translation: this will lead to the elimination of a LOT
> of interprocessor interrupts to invalidate TLB entries. I'll be
> "turning on" the new mechanisms slowly so we can carefully debug
> each step and (hopefully) avoid any problems.
>
(To the rest of the team, Alan and Luoqi already know my opinion.)
I just wanted to "chime in" and say that the new patches are based
on a really good concept, and is much cleaner than the previous
method. Also, many RISC architectures can utilize this
method due to the availability of lots of general registers.
(One could go so far as to have the compiler reserve the
register.) Non-threaded user mode apps could optionally
use the reserved register, but for threaded user mode apps,
that reserved register could also be used as a per-thread
base pointer.
I believe that NT does the above (%fs for X86, and general
register for Alpha.) On PPC, there are several local,
per-processor registers that one could use (but loading a
general register with that per processor register would be
needed for access.) Also, since the PPC has lots of registers,
one could? permanently reserve one of the general registers (r13?).
All in all, this change has the potential for better context
switching time (and less memory/better performance for multi-threaded
processes.) This is a serious, non-trivial movement in the *right*
direction!!! :-). SMP users should be pleased with this movement (I
certainly am!!!)
--
John | Never try to teach a pig to sing,
dy...@iquest.net | it makes one look stupid
jdy...@nc.com | and it irritates the pig.
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